By Topic

Bias temperature stress analysis of ZnO thin film transistors with HfO2 gate dielectrics

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
J. J. Siddiqui ; EECS Department, University of Michigan, Ann Arbor, 48109-2122, USA ; J. D. Phillips ; K. Leedy ; B. Bayraktaroglu

ZnO thin film electronics have received much attention due to the relatively high electron mobility of ZnO thin films in comparison to amorphous silicon (a-Si) and organic thin films. There is significant interest in using ZnO thin film transistors (TFTs), or similar oxides such as InGaZnO and zinc tin oxide, to replace a-Si TFTs in large area display technologies such as active matrix liquid crystal display devices and active matrix organic light-emitting displays where transparency in the visible range and high carrier mobilities are significant advantages. In addition, the integration of high dielectric constant (high-k) dielectrics in ZnO TFTs has demonstrated performance advantages including reduced operating voltage, increased Ion/Ioff ratios, and larger transconductance. HfO2 has emerged as a high-k dielectric of choice for both silicon microelectronics and thin film electronics due to the high dielectric constant (εr ~ 25ε0), low leakage current, and low synthesis temperature. Voltage stability is an important figure of merit for many TFT applications and much work has been done to characterize the voltage stability of a-Si and poly-crystalline silicon (p-Si) TFTs. Extensive Bias-Temperature-Stress (BTS) studies have been carried out on a-Si and p-Si TFTs to track the threshold voltage (VTH), subthreshold slope (S), mobility (μ), and grain boundary trap creation (NTG) over time and to correlate TFT parameter instabilities with physical mechanisms that include charge trapping in the gate oxide and charge state creation in the oxide, interface, and p-Si grain boundaries. Prior studies on the stability of ZnO TFTs have indicated threshold voltage shifts (ΔVTH) with the same polarity as the stress voltage (VSTR) that increase with time and that S remains unchanged below a certain VSTR, but will degrade with time above this- - value. Ability to recover pre-stress characteristics with and without post-stress treatments has also been reported. Further investigation is desired to both understand the device instability behavior dependence on temperature and gate-bias and to determine the physical origins governing the instabilities in this important material system. In this work, the instabilities of HfO2/ZnO TFTs are studied by BTS investigation.

Published in:

Device Research Conference (DRC), 2011 69th Annual

Date of Conference:

20-22 June 2011