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An approach to reduce computational cost in combinatorial logic netlist reliability analysis using circuit clustering and conditional probabilities

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4 Author(s)
Josep Torras Flaquer ; STMicrolectronics, Central CAD and Design Solutions (CCDS), Crolles, France ; Jean Marc Daveau ; Lirida Naviner ; Philippe Roche

We propose a novel approach relying on signal state conditional probabilities and circuit clustering to perform a probabilistic analytical estimation of the reliability of combinatorial logic circuits. This approach uses clustering and joint conditional probabilities to reduce the execution time and matrix size needed. Its effectiveness is demonstrated on a 8 bit Brent Kung adder.

Published in:

2011 IEEE 17th International On-Line Testing Symposium

Date of Conference:

13-15 July 2011