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A new IP core for fast error detection and fault tolerance in COTS-based solid state mass memories

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3 Author(s)
Costenaro, E. ; iRoC Technol., Grenoble, France ; Violante, M. ; Alexandrescu, D.

Commercial-off-the-shelf (COTS) components are crucial for the success of future space missions as, although not being specifically designed for space, they are the only components able to meet the performance requirement that new missions impose to designers. COTS memories are particularly appealing as large memory arrays can be implemented, which can be made immune to radiations by means of cost-effective information redundancy schemes. In this paper, we present an intellectual property (IP) core implementing a (12, 8) Reed-Solomon (RS) code for error mitigation that is suitable for COTS Flash NAND and NOR memories. The main novelty of the proposed scheme consists in its architecture which is based on a shortened Reed-Solomon code with a fast error detection feature. Two implementations have been studied: a fully combinational scheme that provides error detection and correction in the access cycle and a two-stage pipeline with early (in-cycle) error detection a 1-cycle latency correction. The pipelined version presents the specific advantages of minimizing the time penalty associated to a traditional RS implementation. We have characterized the area and timing performance of the proposed architectures in a variety of FPGA implementations, obtaining a maximum frequency of 47 MHz for the combinational implementation and 53 MHz for the pipelined one (in a Virtex 6 FPGA), with a quick 5 ns error detection. In addition, we have characterized the fault resiliency of the proposed schemes with respect to Single Event Transients and Single Event Faults.

Published in:

On-Line Testing Symposium (IOLTS), 2011 IEEE 17th International

Date of Conference:

13-15 July 2011

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