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Selective fault tolerance for finite state machines

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3 Author(s)
Augustin, M. ; Comput. Sci. Inst., BTU Cottbus, Cottbus, Germany ; Gossel, M. ; Kraemer, R.

This paper introduces the concept of Selective Fault Tolerance for sequential circuits. A sequential circuit that is designed according to this method is fault-tolerant for an arbitrarily selected subset of input sequences that are applied in one or more arbitrarily specified states. Once a selected input sequence is applied in a specified state, the circuit guarantees the same degree of fault tolerance as Triple Modular Redundancy (TMR). No fault tolerance is guaranteed in any other case. A simple heuristic algorithm for the design of such circuits is presented and for a benchmark circuit the reduction of area overhead compared to TMR is experimentally determined. The proposed method is a generalization of Selective Fault Tolerance for combinational circuits as described in [1].

Published in:

On-Line Testing Symposium (IOLTS), 2011 IEEE 17th International

Date of Conference:

13-15 July 2011

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