Variation-aware clock network design methodology for ultra-low voltage (ULV) circuits

This paper presents a design methodology for robust and low-energy clock networks for ultra-low voltage (ULV) circuits. We show that both clock slew and skew play important roles in achieving high maximum operating frequency (F
max
) and low clock energy in ULV circuits. In addition, clock networks in ULV circuits are highly sensitive to process variations. We propose a variation-aware methodology that controls both clock skew and slew to maximize F
max
and minimize clock power. Experimental results show that our clock network design method achieves lower energy (more than 20 % savings) at comparable or even higher F
max
compared with the existing methods.