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TLB index-based tagging for cache energy reduction

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3 Author(s)
Jongmin Lee ; Department of Computer Science, Korea Advanced Institute Science and Technology (KAIST), Daejeon, Korea ; Seokin Hong ; Soontae Kim

Conventional cache tag matching is based on addresses to identify correct data in caches. However, this tagging scheme is not efficient because tag bits are unnecessarily large. From our observations, there are not many unique tag bits due to typically small working sets, which are conventionally captured by TLBs. To effectively exploit this fact, we propose TLB index-based cache tagging scheme. This new tagging scheme reduces required number of tag bits to one-fourth of the conventional tagging scheme. The reduced tag bits decrease tag bits array area by 72% and its energy consumption by 58%. From our experiments, our proposed new tagging scheme reduces instruction cache energy consumption by 13% for embedded systems.

Published in:

Low Power Electronics and Design (ISLPED) 2011 International Symposium on

Date of Conference:

1-3 Aug. 2011