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3D Super chip technology to achieve low-power and high-performance system-on-a chip

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1 Author(s)
Koyanagi, M. ; New Ind. Creation Hatchery Center, Tohoku Univ., Sendai, Japan

A new three-dimensional (3D) integration technology based on a reconfigured wafer-to-wafer bonding method called a super-chip integration has been developed to achieve low-power and high-performance system-on-a chip (SoC). A number of known good dies (KGDs) are simultaneously aligned and bonded onto lower chips or wafers with high alignment accuracy by using a new self-assembly technique in a super-chip integration.

Published in:

Low Power Electronics and Design (ISLPED) 2011 International Symposium on

Date of Conference:

1-3 Aug. 2011