By Topic

Pinned to the walls — Impact of packaging and application properties on the memory and power walls

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

The purchase and pricing options are temporarily unavailable. Please try again later.
3 Author(s)
Stanley-Marbell, P. ; IBM Res. - Zurich, Rüschlikon, Switzerland ; Cabezas, V.C. ; Luijten, R.P.

This article presents a study of the impact of packaging on the memory and power walls, in the context of application properties. The analysis is supported by characterizations of 130 hardware designs spanning 30 years, along with both microarchitectural simulation and actual-hardware performance counter measurements of 25 applications. It is shown that if trends in supply pin count (growing as the square root of current) and total packaging pin count (doubling every six years) continue, application memory bandwidth requirements, even in the presence of aggressive cache hierarchies, may limit the number of on-chip threads to under a thousand in 2020.

Published in:

Low Power Electronics and Design (ISLPED) 2011 International Symposium on

Date of Conference:

1-3 Aug. 2011