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Energy minimum operation in a reconfigurable gate-level pipelined and power-gated self synchronous FPGA

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3 Author(s)
Devlin, B. ; Dept. of Electron. Eng., Univ. of Tokyo, Tokyo, Japan ; Ikeda, M. ; Asada, K.

A 65nm self synchronous field programmable gate array (SSFPGA) which uses autonomous gate-level power gating with minimal control circuitry overhead for energy minimum operation is presented. The use of self synchronous signalling allows the FPGA to operate at voltages down to 370mV without any parameter tuning. We show both 2.6× total energy reduction and 6.4× performance improvement at the same time for energy minimum operation compared to the non-power gated SSFPGA, and compared to the latest research 1.8× improvement in power-delay product (PDP) and 2× performance improvement. When compared to a synchronous FPGA in a similar process we are able to show up to 84.6× PDP improvement. We also show energy minimum operation for maximum throughput on the power gated SSFPGA is achieved at 0.6V, 27fJ/operation at 264MHz.

Published in:

Low Power Electronics and Design (ISLPED) 2011 International Symposium on

Date of Conference:

1-3 Aug. 2011