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A 60 GHz Antenna-Referenced Frequency-Locked Loop in 0.13 \mu m CMOS for Wireless Sensor Networks

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2 Author(s)
Kuo-Ken Huang ; Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, USA ; David D. Wentzloff

This paper presents a 60 GHz frequency-locked loop (FLL) for wireless sensor network applications. The FLL incorporates an on-chip patch antenna as both a radiator and a frequency reference, realizing a compact and low-cost solution for non-coherent energy detection radios. To further reduce the size of a wireless sensor node, the area beneath the patch antenna ground plane is utilized for analog and digital baseband circuitry integration. A sensor array was implemented beneath the antenna ground plane to measure the spatial coupling from the antenna to the circuitry beneath it. The FLL is fabricated in a 0.13 μm CMOS technology. The operating frequency is locked to the maximum-efficiency point of the antenna with a mean of 59.34 GHz and standard deviation of 195 MHz over process variation. The circuit and antenna occupies 2.85 mm and consumes 29.6 mW.

Published in:

IEEE Journal of Solid-State Circuits  (Volume:46 ,  Issue: 12 )