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A Novel Binding Algorithm to Reduce Critical Path Delay During High Level Synthesis

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4 Author(s)
Sinha, S. ; Nanyang Technol. Univ., Singapore, Singapore ; Dhawan, U. ; Siew Kei Lam ; Srikanthan, T.

Hardware binding plays an important role in the performance of a design on FPGAs. Good timing performance requires that the hardware binding be as efficient as possible. It is often acceptable to let the area increase within a tolerance limit if the timing could be improved. In this paper, we propose a new hardware binding algorithm.. It performs simultaneous FU and register binding incorporating device-specific delay information for functional units and multiplexers. The proposed approach, implemented within a C to RTL framework has resulted in significant improvement in maximum achievable clock frequency compared to previously proposed Weighted Bipartite Matching and Compatibility Path Based algorithms. The associated increase in area is also within a very tight margin and hence quite acceptable even when there is an area constraint. Also, when compared to WBM and CPB methods, the proposed algorithm improves clock period on average by 17.6% and 9.7% respectively without any penalty in area. When compared with ECPB algorithm, clock period is improved by 5.6% on average at a small area cost of 5.5%.

Published in:

VLSI (ISVLSI), 2011 IEEE Computer Society Annual Symposium on

Date of Conference:

4-6 July 2011

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