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The effects of random variations in the fabrication process have increased significantly with the scaling of technology. This leads to parametric failure of IC performances causing a significant loss of yield. In this work, we propose a statistical design flow to minimize the performance parameter variance due to process and mismatch effects by choosing optimized transistor dimensions. Stochastic MOSFET (SMOS) models are used for statistical simulation of circuits to capture the effects of process variation and mismatch in terms of performance parameter variations. Design of a two-stage OpAmp, in 0.18μm technology, has been used as a case-study in this work.