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Layer-Aware Design Partitioning for Vertical Interconnect Minimization

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3 Author(s)
Ya-Shih Huang ; Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan ; Yang-Hsiang Liu ; Juinn-Dar Huang

Three-dimensional (3D) design technology, which has potential to significantly improve design performance and ease heterogeneous system integration, has been extensively discussed in recent years. This emerging technology allows stacking multiple layers of dies and typically resolves the vertical inter-layer connection issue by through-silicon vias (TSVs). However, TSVs also occupy significant silicon estate as well as incur reliability problems. Therefore, the deployment of TSVs must be very judicious in 3D designs. In this paper, we propose an iterative layer-aware partitioning algorithm, named iLap, for TSV minimization in 3D structures. iLap iteratively applies multi-way min-cut partitioning to gradually divide a given design layer by layer in the bottom-up fashion. Meanwhile, iLap also properly fulfills a specific I/O pad constraint incurred by 3D structures to further improve its outcome. Experimental results show that iLap can reduce the number of TSVs by about 35% as compared to several existing state-of-the-art methods. We believe a good TSV-minimized 3D partitioning solution can serve as a good starting point for further tradeoff operations between TSV count and wirelength.

Published in:

VLSI (ISVLSI), 2011 IEEE Computer Society Annual Symposium on

Date of Conference:

4-6 July 2011