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Minimization of Circuit Delay and Power through Gate Sizing and Threshold Voltage Assignment

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4 Author(s)
Shuzhe Zhou ; Dept. of Comput. Sci. & Technol., Tsinghua Univ., Beijing, China ; Hailong Yao ; Qiang Zhou ; Yici Cai

Low power and high performance are the main pursuits of circuit optimization. Circuit optimization through simultaneous gate sizing and threshold voltage (Vt) assignment has received much attention from academia and industry. A method of minimizing both delay and power consumption is presented in this paper. Guided by static timing analysis, an iterative refinement method on delay is proposed based on the classic dynamic programming (DP) based framework in. Then, power is further optimized under optimized delay constraint. Our main contributions include: (1) an enhanced timing optimization algorithm with improved accuracy and better solution quality, (2) a detailed description of multipliers selection method and delay/power splitting approaches, and (3) an integration of the unconstrained timing optimization and delay constrained power optimization, which enables better performance and less power consumption. Experimental results show that our method outperforms the original algorithm by 20% in delay optimization. In addition, under a tighter delay constraint, we can further reduce power consumption by 3% on average.

Published in:

VLSI (ISVLSI), 2011 IEEE Computer Society Annual Symposium on

Date of Conference:

4-6 July 2011