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A 16-Gbps 9mW Transmitter with FFE in 90nm CMOS Technology for Off-Chip Communication

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5 Author(s)
S. R. Sant ; Dept. of Electr. Eng., Indian Inst. of Technol. Bombay, Mumbai, India ; S. S. Waikar ; M. Dave ; M. Shojaei Baghini
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This paper presents a low power 16 Gbps backplane transmitter for chip-to-chip communication, designed and optimized in 90 nm CMOS process with supply voltage of 1V. The proposed 3-tap transmitter incorporates a new quarter-rate architecture for feed-forward equalization at the transmitter end. Key features of this architecture are: most of the circuit modules operate at quarter-rate and data serializer as well as feed forward equalizer are merged together in one module. Both the features enable low power operation. Simulation results show that 16 Gbps data rate can be achieved over 30 cm FR4 line consuming 9 mW average power. Power per Gbps consumed by the proposed architecture is 62% less as compared to state of the art FFE equalizer realized in the same technology.

Published in:

2011 IEEE Computer Society Annual Symposium on VLSI

Date of Conference:

4-6 July 2011