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Vertically-stacked bottom- and top- gate polycrystalline silicon TFTs for three dimensional integrated circuit

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6 Author(s)
Lee, I-Che ; Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan ; Tsung-Che Tsai ; Chun-Chien Tsai ; Yang, Po-Yu
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A high-performance poly-Si TFT with bottom-gate structure and a top-gate poly-Si TFT were vertically stacked for three dimensional integrated circuit. Consequently, the n-channel poly-Si TFTs with bottom-gate structure on the bottom layer showed considerably improved electrical characteristics, such as a high field effect mobility of 390 cm2/V-s due to the large lateral grain formed in the channel. The vertically stacked p-channel poly-Si TFTs with top-gate structure on the top layer showed a high field effect mobility of 131 cm2/V-s. Therefore, the proposed structure is very suitable for future 3D-IC and nano-device application.

Published in:

Nanoelectronics Conference (INEC), 2011 IEEE 4th International

Date of Conference:

21-24 June 2011

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