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Investigation of the dimension effects of 30-nm below multiple-gate SOI MOSFETs by TCAD simulation

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2 Author(s)
Keng-Ming Liu ; Dept. of Electr. Eng., Nat. Dong Hwa Univ., Hualien, Taiwan ; Yung-Yu Hsieh

In this paper we use the commercial semiconductor device simulator, Sentaurus, to simulate the electrical characteristics of sub-30nm multiple-gate (MG) SOI MOSFETs. The gate configurations of the simulated MG SOI MOSFETs include: single-gate (SG), double-gate (DG), triple-gate (TG), and gate-all-around (GAA). We examine the effects of the dimensions of the gate length, fin height, fin width, and the transport models for each gate configuration. The simulation results indicate that as the gate length scales down to 15 nm below, only certain gate configurations with specific fin cross-section dimensions can meet the device requirements.

Published in:

Nanoelectronics Conference (INEC), 2011 IEEE 4th International

Date of Conference:

21-24 June 2011

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