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It is recognized that the conventional model for metal-ferroelectric-insulator-semiconductor field-effect transistors (MFIS-FETs) always neglects the history-dependent electric field effect of the ferroelectric layer. In this paper, an improved model combining the dipole switching theory with the silicon physics of metal-oxide-semiconductor structures and with Pao and Sah's double integral, respectively, is proposed to describe the capacitance-gate voltage (C -VG) characteristics of MFIS structures and the drain current-gate voltage (ID- VGS) and drain current-drain voltage (ID-VDS) characteristics of MFIS-FETs. Close agreement between modeling and experimental results confirms the validity of the improved model. The influence of the gate voltage, SiO2 layer thickness, and interface layer thickness on the C-VG, ID-VGS, and ID-VDS characteristics are simulated and discussed. The memory windows of C-VG and ID-VGS characteristics, as well as the ID -VDS characteristics, increase with increasing gate voltage. The thicker the SiO2 or interface layer, the worse the transistor characteristics. This paper is expected to provide some guidance to the design and performance improvement of MFIS structure devices. In addition, the mathematical description can be easily combined with electronic design automation software for circuit simulation.