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A Chip-ID generating circuit for dependable LSI using random address errors on embedded SRAM and on-chip memory BIST

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6 Author(s)
Fujiwara, H. ; Renesas Electron. Corp., Tokyo, Japan ; Yabuuchi, M. ; Nakano, H. ; Kawai, H.
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A chip-ID generating scheme with high-tamper resistance is proposed. This enables to extract a unique finger print from each chip by using random failure bits in an SRAM under the ID generation mode, and on-chip memory BIST. The stability and average of Humming distance of 128 bit ID become 99.9999999% and 63.9, respectively. The proposed scheme does not require any additional hardware IPs.

Published in:

VLSI Circuits (VLSIC), 2011 Symposium on

Date of Conference:

15-17 June 2011