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A 45nm 48-core IA processor with variation-aware scheduling and optimal core mapping

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7 Author(s)
Saurabh Dighe ; Microprocessor Research, Intel Labs, Intel Corporation, USA ; Sumeet Gupta ; Vivek De ; Sriram Vangal
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This paper describes energy benefits from variation-aware dynamic voltage frequency scaling (VA-DVFS) schemes & presents measured within-die core-to-core maximum operational frequency (Fmax), leakage & thermal variations for a 45nm 48-core IA processor. On-package voltage regulators (OPVR) supplying 8 independent voltage rails combined with 24 frequency islands enable VA-DVFS to exploit these variations for improved performance or energy efficiency. Measurements with industry standard benchmarks on a real system show that the proposed VA-DVFS & optimal core mapping schemes (VA-L & VA-LV) improve core computation energy by up to 21% & chip energy by up to 14.5% across varying voltage/frequency (V/F) operating points & core counts.

Published in:

VLSI Circuits (VLSIC), 2011 Symposium on

Date of Conference:

15-17 June 2011