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A 20-Gb/s, 0.66-pJ/bit serial receiver with 2-stage continuous-time linear equalizer and 1-tap decision feedback equalizer in 45nm SOI CMOS

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2 Author(s)
Proesel, J.E. ; T.J. Watson Res. Center, IBM, Yorktown Heights, NY, USA ; Dickson, T.O.

A power-efficient equalizing serial receiver, including a 2-stage continuous-time linear equalizer (CTLE) and 1-tap decision feedback equalizer (DFE), is reported operating at data rates of up to 20 Gb/s. The DFE adopts a half-rate speculative architecture without explicit summing amplifiers by injecting offset-controlling currents directly into StrongARM sampling latches. At 20 Gb/s, a PCB trace with 26.3 dB of loss is equalized while consuming 13.2 mW (0.66 pJ/bit).

Published in:

VLSI Circuits (VLSIC), 2011 Symposium on

Date of Conference:

15-17 June 2011