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We present a fully integrated phase-change memory chip serving both as a 2b/cell technology demonstrator and benchmarking platform for higher density multi-level cell (MLC). The 256M-cell memory achieves 2b/cell at a raw BER ~ 2 10-4. For exploring the 2+b/cell regime, the peripheral readout and programming circuitry supports MLC up to 4b/cell. The iterative programming of the MLC cells is optimized by choosing from different modes (e.g., current vs. voltage controlled write pulse) and fine-tuning the programmable parameters. The 6b readout ADC offers high-throughput (690Mb/s) characterization of PCM arrays directly on-chip, thereby allowing studies of drift and noise.