By Topic

A 512Mb phase-change memory (PCM) in 90nm CMOS achieving 2b/cell

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

10 Author(s)
Close, G.F. ; IBM Res. - Zurich, Zurich, Switzerland ; Frey, U. ; Morrish, J. ; Jordan, R.
more authors

We present a fully integrated phase-change memory chip serving both as a 2b/cell technology demonstrator and benchmarking platform for higher density multi-level cell (MLC). The 256M-cell memory achieves 2b/cell at a raw BER ~ 2 10-4. For exploring the 2+b/cell regime, the peripheral readout and programming circuitry supports MLC up to 4b/cell. The iterative programming of the MLC cells is optimized by choosing from different modes (e.g., current vs. voltage controlled write pulse) and fine-tuning the programmable parameters. The 6b readout ADC offers high-throughput (690Mb/s) characterization of PCM arrays directly on-chip, thereby allowing studies of drift and noise.

Published in:

VLSI Circuits (VLSIC), 2011 Symposium on

Date of Conference:

15-17 June 2011