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A 21nm high performance 64Gb MLC NAND flash memory with 400MB/s asynchronous toggle DDR interface

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21 Author(s)
Chulbum Kim ; Flash Memory Design Team, Samsung Electron., Hwasung, South Korea ; Jinho Ryu ; Taesung Lee ; Hyeonggon Kim
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A monolithic 64Gb MLC NAND flash based on 21nm process technology has been developed for the first time. The device consists of 4-plane arrays and provides page size of up to 32KB. It also features a newly developed DDR interface that can support up to the maximum bandwidth of 400MB/s. To address performance and reliability, on-chip randomizer, soft data readout, and incremental bit line precharge scheme have been developed.

Published in:

VLSI Circuits (VLSIC), 2011 Symposium on

Date of Conference:

15-17 June 2011