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A 27% active-power-reduced 40-nm CMOS multimedia SoC with adaptive voltage scaling using distributed universal delay lines

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15 Author(s)
Yoshifumi Ikenaga ; Renesas Electronics Corporation, 1753, Shimonumabe, Nakahara-ku, Kawasaki, Kanagawa 211-8668, Japan ; Masahiro Nomura ; Shuji Suenaga ; Hideo Sonohara
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AVS technique for extremely scaled SoCs has been developed. To reduce design cost, we have developed a supply voltage control scheme employing universal delay line (UDL), rather than a replica delay line, for monitoring the critical path delay (TCRIT). The UDL can be used in any product without any need for customizing. The error to TCRIT is as small as that with replica delay line. We have shown that 40-nm CMOS SoCs using our AVS can reduce active power by 27%.

Published in:

VLSI Circuits (VLSIC), 2011 Symposium on

Date of Conference:

15-17 June 2011