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AVS technique for extremely scaled SoCs has been developed. To reduce design cost, we have developed a supply voltage control scheme employing universal delay line (UDL), rather than a replica delay line, for monitoring the critical path delay (TCRIT). The UDL can be used in any product without any need for customizing. The error to TCRIT is as small as that with replica delay line. We have shown that 40-nm CMOS SoCs using our AVS can reduce active power by 27%.