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The implementation of complex, high-performance functionality in nano-CMOS technologies faces significant design and test challenges related to the increased susceptibility to process variations and environmental or operation-dependent disturbances. This paper describes the application of semi-empirical propagation delay variation models to estimate the effect of process variations on the timing response of nanometer digital circuits. Experimental results based on electrical simulations of a circuit designed in 65nm CMOS technology are presented demonstrating that the models can be used for the analytical derivation of delay variability windows associated to process variations. This information can be used during both the design and test processes. On one hand, it allows the robustness of a given circuit in the presence of process variations to be evaluated. On the other hand, it allows the boundaries between expected functional windows and those associated to abnormal behaviors due to delay faults to be defined. The main advantage of the proposed approach is that the effect of process variations on circuits' performance can be jointly analyzed with those of power supply voltage and temperature variations.