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Using the array test pattern, gate current through the tunnel oxide on the order of 10-16 A can be measured for about 1 000 000 transistors within 4 min. Because this test pattern can be fabricated by simple processes and its peripheral circuits are simple structures, the tunnel dielectric formation method and condition can be changed drastically. It was found that anomalous stress-induced leakage current (SILC) appears or disappears by applying electrical stress, and it is annealed out during a relatively high temperature measurement at 60 °C. Random telegraph signal in SILC can be observed in some transistors. These are very similar phenomena observed in Flash memory cells. We consider that, using this test pattern for the development of tunnel oxide, we can clarify the origin of anomalous SILC and promote the downscaling of tunnel oxide thickness.