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TRAM: a design methodology for high-performance, easily testable, multimegabit RAMs

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2 Author(s)
Jarwala, N.T. ; Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA ; Pradhan, D.K.

An architecture is proposed for multimegabit dynamic RAMs (random-access memories) that achieves higher testability and performance than the conventional four-quadrant RAMs. Applying the principle of divide and conquer, the RAM is partitioned into modules, each appearing as the leaf node of a binary interconnect network. Such a network carries the address/data/control bus, permitting the nodes to communicate among themselves as well as with the outside world. This architecture is shown to be easily testable. Parallelism in testing and partial self-test result in a large savings of testing time; the savings is independent of the test algorithm used. Unlike other testability schemes, this approach promises improved performance with only a small increase in chip area. It is also shown that the architecture is easily partionable and restructurable, with potential for yield and reliability improvement

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Computers, IEEE Transactions on  (Volume:37 ,  Issue: 10 )