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TSV process optimization for reduced device impact on 28nm CMOS

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16 Author(s)
Yu, C.L. ; R&D, Integrated Interconnect & Packaging Div., tsmc, Hsinchu, Taiwan ; Chang, C.H. ; Wang, H.Y. ; Chang, J.H.
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A through-silicon-via (TSV) process is demonstrated on 28nm CMOS baseline with good electrical performance and low cost. TSV leakage, yield, C-V flat-band shift, Cu contamination, and reliability are significantly improved via process optimization. The preferred TSV processing could relax TSV stress and minimize keep-out zone (KOZ). In this study, we also address the impact of multiple-TSVs additive stress impact, TSV signal coupling effect, and TSV depletion impact to assess the power-TSV plug cell in design practice.

Published in:

VLSI Technology (VLSIT), 2011 Symposium on

Date of Conference:

14-16 June 2011