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A through-silicon-via (TSV) process is demonstrated on 28nm CMOS baseline with good electrical performance and low cost. TSV leakage, yield, C-V flat-band shift, Cu contamination, and reliability are significantly improved via process optimization. The preferred TSV processing could relax TSV stress and minimize keep-out zone (KOZ). In this study, we also address the impact of multiple-TSVs additive stress impact, TSV signal coupling effect, and TSV depletion impact to assess the power-TSV plug cell in design practice.