By Topic

Non-Gaussian distribution of SRAM read current and design impact to low power memory using Voltage Acceleration Method

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

15 Author(s)
Wang, J. ; Qualcomm Inc., San Diego, CA, USA ; Ping Liu ; Yandong Gao ; Deshmukh, P.
more authors

SRAM read current tail distribution beyond 6s was studied using Voltage Acceleration Method (VAM). For the first time, non-Gaussian distribution of SRAM and ROM read current was confirmed with direct measurements on actual silicon. Data shows that conventional assumption of Gaussian distribution in read current is inaccurate especially at low Vdd and cold temperature conditions for low power memory in 28nm and beyond technology nodes. In 28nm, this inaccuracy would lead to 2× bit access delay penalty.

Published in:

VLSI Technology (VLSIT), 2011 Symposium on

Date of Conference:

14-16 June 2011