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Scaling of SOI FinFETs down to fin width of 4 nm for the 10nm technology node

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8 Author(s)
Chang, J.B. ; T.J. Watson Res. Center, IBM Res., Yorktown Heights, NY, USA ; Guillorn, M. ; Solomon, P.M. ; Lin, C.-H.
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Using a novel replacement gate SOI FinFET device structure, we have fabricated FinFETs with fin width (DFin) of 4 nm, fin pitch (FP) of 40 nm, and gate length (LG) of 20 nm. With this structure, we have achieved arrays of thousands of fins for DFin down to 4 nm with robust yield and structural integrity. We observe performance degradation, increased variability, and VT shift as DFin is reduced. Capacitance measurements agree with quantum confinement behavior which has been predicted to pose a fundamental limit to scaling FinFETs below 10 nm LG.

Published in:

VLSI Technology (VLSIT), 2011 Symposium on

Date of Conference:

14-16 June 2011

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