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Multi-level NAND flash memories with a 20nm design rule have been successfully developed for the first time. A 20nm rule wordline (WL) and bitline (BL) direction have been realized by Spacer Patterning Technology (SPT) of ArF immersion lithography. Key integration technologies include WL airgap with separate gate etch process and optimized control gate (CG) poly deposition process. In addition, many physical and electrical challenges are successfully demonstrated to overcome scaling limit of 20nm technology.
VLSI Technology (VLSIT), 2011 Symposium on
Date of Conference: 14-16 June 2011