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An optimal multiplication algorithm on reconfigurable mesh

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3 Author(s)
Ju-Wook Jang ; Dept. of Electr. Eng., Sogang Univ., Seoul, South Korea ; Heonchul Park ; V. K. Prasanna

An O(1) time algorithm to multiply two K-bit binary numbers using an N×N bit-model of reconfigurable mesh is shown. It uses optimal mesh size and it improves previously known results for multiplication on the reconfigurable mesh. The result is obtained by using novel techniques for data representation and data movement and using multidimensional Rader Transform. The algorithm is extended to result in AT2 optimality over 1⩽t⩽√N in a variant of the bit-model of VLSI

Published in:

IEEE Transactions on Parallel and Distributed Systems  (Volume:8 ,  Issue: 5 )