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We propose an approach to monolithically integrate bulk germanium (Ge) or Ge quantum wells with silicon-on-insulator (SOI) waveguides through selective epitaxy and direct butt coupling. To prevent lateral epitaxial growth during the selective epitaxy, a dielectric insulating spacer layer is deposited on the sidewall facet of the SOI waveguide. With an SiO2 spacer that is 20 nm thick, the additional insertion loss penalty can be as low as 0.13 dB. We also propose and demonstrate a robust, reliable, and complementary metal-oxide-semiconductor (CMOS)-compatible fabrication process to realize sub-30-nm spacers.