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Simulations of NoC topologies for generalized hierarchical completely-connected networks

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1 Author(s)
Takabatake, T. ; Dept. of Inf. Sci., Shonan Inst. of Technol., Fujisawa, Japan

The density of integration in a single chip has progressed by use of the deep submicron of VLSI design rule. Systems on a chip (for short, SoCs), i.e., several functional cores being integrated in a single chip, have become the mainstream technology. On the other hand, A Network on a Chip (NoC), i.e., a communication-centric platform, offers an on-chip interconnection network. The NoC is one of the on-chip communication systems. The NoC is used in place of conventional shared bus systems. There are many NoC topologies for connecting cores to each other, such as Mesh, Ring, Spidergon, and so on. To evaluate the NoC topologies, a simulation based approach was used for the modeling and analysis of the topologies. However, some properties of the topologies could affect the performance of the NoC systems. In this paper, we present the performances of the topologies about the communication aspects by the simulation based approach. In particular, Generalized Hierarchical Completely-Connected Networks (HCC) as the NoC topology is presented. An experimental study is conducted to compare the HCC with the other topologies. Simulation results show that the HCC has enough performance to be used by the NoC topology.

Published in:

Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), 2011 6th International Workshop on

Date of Conference:

20-22 June 2011