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Dynamic circuit design techniques can provide high speed operation at lower silicon area requirements, compared to full static CMOS designs. In this paper, we present a memoryless pipeline dynamic design technique with a pre-evaluation phase hidden inside the precharge phase. The combinational logic is implemented with dynamic circuits that offer the desirable high speed operation while the memory elements are eliminated due to an intelligent three phase clocking scheme. According to simulation results high quality designs can be achieved, in terms of performance, energy consumption and area, with respect to alternative dynamic design styles.