By Topic

An offset cancellation technique for comparators using body-voltage trimming

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Mashhadi, S.B. ; Dept. of Electr. Eng., Ferdowsi Univ. of Mashhad, Mashhad, Iran ; Nasrollaholosseini, S.H. ; Sepehrian, H. ; Lotfi, R.

In this paper an offset cancellation technique based on body voltage trimming is presented to be used in the comparators employed in Flash or Successive-Approximation analog-to-digital converters. The proposed offset cancellation is achieved by body voltage adjustment using low-power simple analog control feedback circuit without any additional capacitive loading at the comparator output. The accuracy of the proposed technique is higher than its digital calibration counterparts due to its analog nature. The technique is employed in the design of a 6-bit 1-GSps Flash ADC in 0.18 μm CMOS technology. Simulation results show that using the proposed technique the standard deviation of the comparator offset is significantly reduced from 28 mV to 750 μV operating at 1-GHz with only 25 μW power in offset cancellation. The cancellation scheme generally improves the ENOB by approximately 0.5 bit after cancellation.

Published in:

New Circuits and Systems Conference (NEWCAS), 2011 IEEE 9th International

Date of Conference:

26-29 June 2011