Area efficient switch box topologies for 3D FPGAs

The dense routing channels of long global interconnects in today's high performance Field Programmable Gate Arrays (FPGAs), as principle counterpart for ASICs, is a dominant factor in continuous increase in the delay, power, and also the chip area. Using the three dimensional (3D) technology is an essential and also attractive technique to solve these problems. However, the limitation on the number of through silicon vias (TSVs) is one of the most important challenges of 3D FPGAs. This paper proposes two modified topologies for the 3D switch boxes (SBs), named Universal-MTwist and Wilton-MTwist, which increase the efficient use of TSVs. The simulation results manifest that the two new SB topologies efficiently reduce the number of TSVs 60% and 66%, respectively. Additionally, the use of them reduces the horizontal channel width 7% and 6%, respectively, compared to the 3D Disjoint SB. Meanwhile, the delay remains almost the same.