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Design and FPGA implementation of stochastic turbo decoder

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3 Author(s)
Quang Trung Dong ; Institut Telecom, Telecom Bretagne, CNRS Lab-STICC UMR 3192, Technopôle Brest Iroise, CS 83818 29238 Brest, Université Européenne de Bretagne, France ; Matthieu Arzel ; Christophe Jégo

Stochastic decoding that is inspired by stochastic computation is an alternative technique for decoding of error-correcting codes. The extension of this approach to decode convolutional codes and turbo codes is discussed in this article. The switching activity sensitivity is circumvented and the latching problem is reduced by transforming the stochastic additions into stochastic multiplications in the exponential domain and using multiple streams with deterministic shufflers. The number of decoding cycles is thus considerably reduced with no performance degradation. Stochastic decoding, previously applied to the decoding of LDPC codes, can now be applied to decoding of turbo codes. In addition, the first hardware architecture for stochastic decoding of turbo codes is presented. The proposed architecture makes fully-parallel turbo decoding viable on FPGA devices. Results demonstrate the potential of stochastic decoding to implement fully-parallel turbo decoders.

Published in:

New Circuits and Systems Conference (NEWCAS), 2011 IEEE 9th International

Date of Conference:

26-29 June 2011