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Compact low-power 7-bit 2.6 GS/s 65 nm CMOS ADC for 60 GHz applications

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5 Author(s)
Ku, I. ; Dept. of Electr. Eng., Univ. of California, Los Angeles, CA, USA ; Xu, Z. ; Kuan, Y.C. ; Wang, Y.H.
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A 7-bit, 2.6 GS/s time-interleaved analogue-to-digital converter (ADC) for 60 GHz applications is designed and fabricated in 65 nm CMOS. The proposed subranging ADC architecture with time-shifting track-and-hold and two-phase amplification and encoding significantly enhances the speed of individual ADCs and reduces the number of interleaved channels to only four. At 2.6 GS/s sampling rate with a 1.355 GHz input signal, the ADC achieves an effective number of bits of 5.5 bits. Its core occupies 0.3 mm2 chip area and draws 45 mA current from a 1 V supply.

Published in:

Electronics Letters  (Volume:47 ,  Issue: 16 )