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This paper presents a pole-zero placement approach for designing arbitrary-order time-mode filters for anti-imaging (reconstruction) applications. One application is for phase-domain sigma-delta modulation involving digital-to-time converters. The time-mode filters are constructed from an th-order type-II PLL single-loop feedback structure involving an active loop filter of order . The tradeoffs in terms of PLL order, noise bandwidth, settling- and lock-time, and the impact of the voltage-controlled oscillator (VCO) phase noise on the performance of the time-mode filter are investigated. A sixth-order PLL is designed and fabricated on a printed circuit board and is used to validate the proposed synthesis method. In addition, an all-digital phase stimulus generation method well suited to a digital scan-based design-for-test (DFT) approach for testing the frequency response behavior of time-mode filters and other PLL-based designs is proposed.