By Topic

Performance evaluation of a Turbo Codec with Log-MAP algorithm on FPGA and CPU

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Moncayo, H.I.R. ; Electr. Eng. Dept., Univ. of North Dakota, Grand Forks, ND, USA ; Kaabouch, N. ; Wen-chen Hu ; Anlei Wang

It has been demonstrated that transmission systems using Turbo codes can achieve performance close to the Shannon limit. Although these codes were introduced two decades ago, their hardware implementations are still challenging because of the complexity of their equations. This paper presents a Field Programmable Gate Array-based implementation of a Turbo Codec system. This system includes an encoder and a decoder based on the Log-MAP algorithm. The implementation is simulated using ModelSim software and the results are compared to the results of the software-based implementation. These results show that the FPGA-based Turbo Codec is able to estimate correctly the information sequence; therefore its BER performance is comparable to the software-based implementation. However, the results of the comparison also show that the FPGA-based system is faster and consumes less energy that the software-based system.

Published in:

Electro/Information Technology (EIT), 2011 IEEE International Conference on

Date of Conference:

15-17 May 2011