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A novel 9T SRAM design in sub-threshold region

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2 Author(s)
Ramani, A.R. ; Dept. of Electr. & Comput. Eng., Illinois Inst. of Technol., Chicago, IL, USA ; Ken Choi

With technology scaling, lower power operation has become one of the key areas of importance in VLSI Design. Lowering power supply is a very good and effective technique for power reduction. Scaling the supply voltage into the sub-threshold region for low power operation is possible. Power reduction in memory circuits with a little compromise on performance is very useful as they form a major part of a digital chip. In this paper, operation of various SRAM designs in sub-threshold region is examined and the ones which overcome the challenges that arise from operating in the sub-threshold region are also explained. Among the chosen designs for performance evaluation, the successful designs were the ones which resulted in proper read and write. The 7T SRAM and 8T SRAM came up as the best among the selected ones for write and read respectively. In this paper, a new 9T SRAM design is proposed combining the advantages of these two and hence better overall performance. In case of write, the PDP of proposed 9T SRAM design is 2.80% less than the 7T SRAM, 4.48 % less than 8T SRAM, 5.64% less than 9T SRAM design and 8.5 % less than 11T SRAM. Similarly, the savings in PDP during read is 44.8 % less than 7T SRAM and 66.18 % less than 9T SRAM. It is almost same as in the 8T Design. Though PDP of the proposed design is greater than that of the 11T design, the reduced RSNM of 11T design makes it inferior the proposed design when operated in the sub-threshold region.

Published in:

Electro/Information Technology (EIT), 2011 IEEE International Conference on

Date of Conference:

15-17 May 2011