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In deeply scaled CMOS technologies, two major non-ideal factors threaten the survival of the CMOS, i) PVT (process, voltage, and temperature) variations and ii) leakage power consumption. In this paper, we propose a novel process monitoring circuit for low power applications. The proposed circuit is immune to voltage and temperature variation and achieves lower power consumption compared to a previous process monitoring circuit. The proposed process monitoring circuit is implemented using 45nm technology, and the proposed design reduces power consumption by 67% and area by 35.2% compared to the process monitoring circuit previously used.