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Efficient Hardware Accelerators for the Computation of Tchebichef Moments

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4 Author(s)
Kah-Hyong Chang ; Dept. of Electr. Eng., Univ. of Malaya, Kuala Lumpur, Malaysia ; Paramesran, R. ; Asli, B.H.S. ; Chern-Loon Lim

Moments extraction from high resolution images in real time may require a large amount of hardware resources. Using a direct method may involve a critically high operating frequency. This paper presents two improved digital-filter based moment accelerators, as exemplified by a Tchebichef moments computation engine, to introduce features that contribute to an area-efficient and timing-efficient accelerator design. The design of the accelerators invariably consists of two on-chip units: the digital Alter and the matrix multiplication units. Among the features introduced are: a data-shifting means, a filter load distribution method, a reduced set of column filters, sectioned left shifters, a double-line buffer, time-multiplexed and pipelined matrix multiplication sections, and multichip amenable features. A total of 98 frames of test data from high definition videos, real and synthetic images are used in the functional tests. The single-chip field-programmable gate array implementation results show the successful realizations of accelerators capable of moment computations of (31, 31) orders, at 50 frames of 1920 × 1080 8-bit pixels per second, and (63, 63) orders, at 30 frames of 512 × 512 pixels per second. These performances have exceeded that of existing multichip and multiplatform designs.

Published in:

Circuits and Systems for Video Technology, IEEE Transactions on  (Volume:22 ,  Issue: 3 )