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A Low Cost Calibrated DAC for High-Resolution Video Display System

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2 Author(s)
Meng-Hung Shen ; Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan ; Po-Chiun Huang

This paper presents a digitally enhanced strategy for current-steering digital-to-analog converters (DACs) applied to video systems. The linearity error introduced by the wittingly small current sources is evaluated by an on-chip built-in self-test scheme, which comprises a shared CalDAC, a BiasDAC, and a digital controller. Two current tuning loops are involved for error detection and compensation. Detection range of the current deviation is expanded by utilizing the differential structure and digital signal processor (DSP). For a 12-bit DAC prototype realized in 90-nm CMOS process, about 80% gate area reduction of current source array is achieved compared with the case relying on intrinsic matching only. Measurement results demonstrate that the calibrated converter achieves fully 12-bit linearity with both DNL and INL less than 0.5 LSB. At 400-MS/s update rate, the spurious-free dynamic range is 59 dB within 30 MHz bandwidth.

Published in:

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:20 ,  Issue: 9 )

Date of Publication:

Sept. 2012

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