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Modification of the 1-tap parallel look-ahead decision feedback equalizer (DFE) architecture is developed using Boolean algebra to enable its operation at 80 Gbps and beyond. Measurement techniques which can be generally applied to the testing of this as well as to other DFE architectures are devised. The equalizer's wide band clock distribution network enables its operation from 25 to 80 Gbps. The equalizer is designed in a 0.13μm SiGe:C BiCMOS technology, dissipates 4W and occupies 2mm2.
Date of Conference: 5-10 June 2011