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A 2.5-Gb/s On-Chip Interconnect Transceiver With Crosstalk and ISI Equalizer in 130 nm CMOS

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3 Author(s)
Jaewon Lee ; Dept. of Electr. Eng., KAIST, Daejeon, South Korea ; Woojae Lee ; SeongHwan Cho

In this paper, a crosstalk compensation scheme for high speed single-ended on-chip signaling is presented. To reduce the effect of crosstalk in bandwidth enhanced channel employing capacitively driven interconnect, a crosstalk feed-forward equalizer is proposed, which compensates for the low-pass nature of the crosstalk. The proposed scheme is verified using a three-channel 10 mm on-chip interconnect implemented in 130 nm CMOS process. Measurement results show that the proposed transceiver effectively removes the crosstalk for data rates of up to 2.5-Gb/s while consuming 0.96 mW, which corresponds to energy efficiency of 0.41 pJ/bit.

Published in:

Circuits and Systems I: Regular Papers, IEEE Transactions on  (Volume:59 ,  Issue: 1 )