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An extended true-single-phase-clock (E-TSPC) based divide-by-2/3 counter design for low supply voltage and low power consumption applications is presented. By using a wired or scheme; only one transistor is needed to implement both the counting logic and the mode selection control. This can enhance the working frequency of the counter due to a reduced critical path between the E-TSPC flip flops (FFs). Since the number of transistor stacking between the power rails is kept at merely two, the proposed design is sustainable to low VDD operations (531 MHz at 0.6 V VDD) for the power saving purpose. Simulation results show that compared with two classic E-TSPC based designs in 0.18 m process technology, as much as 16.4% in operation speed and 39% in power-delay-product can be achieved by the proposed design.
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on (Volume:20 , Issue: 9 )
Date of Publication: Sept. 2012