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A CMOS low power, wide dynamic range RSSI with integrated AGC loop

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5 Author(s)
Qianqian Lei ; Dept. of Appl. Electron., Xi''an Univ. of Technol., Xi''an, China ; Min Lin ; Miao Peng ; Zhiming Chen
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A low voltage low power CMOS limiter and received signal strength indicator (RSSI) with integrated automatic gain control (AGC) loop are designed using TSMC 0.13um CMOS technology. The limiter uses six-stage amplifier architecture for minimum power consideration achieves 56dB gain and 17MHz bandwidth. The RSSI has a dynamic range more than 60dB, and the RSSI linearity error is within ±0.5dB for an input power from -65dBm to -8dBm. The RSSI output voltage is from 0.2V to 1V and the slope of the curve is 14.28mV/dB. The RSSI with integrated AGC loop draws 1.5 mA (I and Q paths) from a 1.2V single supply, including limiters, RSSI and comparators.

Published in:

Anti-Counterfeiting, Security and Identification (ASID), 2011 IEEE International Conference on

Date of Conference:

24-26 June 2011