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Energy Efficient Adiabatic Logic for Low Power VLSI Applications

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2 Author(s)
Atul Kumar Maurya ; Dept. of Electron. & Commun. Eng., Nat. Inst. of Technol., Hamirpur, India ; Gagnesh Kumar

This paper proposes a Adder circuit based on energy efficient two-phase clocked adiabatic logic. a simulative investigation on the proposed 1-bit full adder has been implemented with the proposed technique and thence compared with standard CMOS, Positive Feedback Adiabatic Logic (PFAL) and Two-Phase Adiabatic Static Clocked Logic (2PASCL) respectively. Comparison has shown a significant power saving to the extent of 70% in case of proposed technique as compared to CMOS logic in 10 to 200MHz transition frequency range.

Published in:

Communication Systems and Network Technologies (CSNT), 2011 International Conference on

Date of Conference:

3-5 June 2011